1. Field of Invention
The present invention relates to a method for manufacturing a semiconductor structure, in particular, to a method for manufacturing a high-performance semiconductor structure with a replacement gate process and a stress memorization technique.
2. Description of Prior Art
It is well known that stress is applied to and improves properties of a field effect transistor (FET). When applied in a longitudinal direction of a channel (i. e. a direction of electric current), tensile stress increases mobility of electrons (i. e. a driving current of nFET), and compressive stress increases mobility of holes (i. e. a driving current of pFET).
One of the approaches for providing such stress is so-called SMT (stress memorization technique), which comprises forming a material having intrinsic stress, such as silicon nitride, at various locations of a semiconductor structure, for example above a channel region; annealing so that the stress is memorized at the respective locations, such as a gate region or an extension region; and removing the stress material. Thus, the stress remains and increases mobility of electrons or holes, which in turn improves overall properties of the semiconductor structure.
Up to now, the prior-art stress memorization technique is used in a gate-first process in which a stress material is first formed and then removed after formation of a gate. A part of the stress introduced by a layer of the stress material is offset by the gate conductor formed previously, which diminishes a stress memorization effect.
Therefore, there still needs a stress memorization technique which is compatible with a gate-last process (referred also as a replacement gate process) and has the effect of further enhancing stress.